Chip Artwork

 Artistry of a different sort.

Software Used:

Mentor Graphics - Schematic and layout design

bmp2cif - Custom script to translate images to layout files.

gds2pov - Program to generate 3D scenes of chip layouts

POV-Ray - Renders 3D scenes


 Starting in January 2008, I started taking the IC Design Lab I course. The finished product of this class is a custom integrated circuit that will be manufactured through MOSIS. This chip will be fabricated during the summer of 2008 and will be done in August. We will be using the AMI C5N 0.5um process on a MOSIS Tiny Chip, which is 1.5mm square.

The chip we designed is a 32 bit serial multiplier. The implementation is very simple and the actual utility of the chip is low. Our group picked this project because we wanted to familiarize ourselves with a different design flow while not overloading ourselves on a difficult layout job. The resulting layout of the serial multiplier is very compact, taking up about 0.39 mm on each side. After this layout was placed in the teacher-supplied pad frame, a lot of extra space remained. We decided to have some fun with this and put some graphics in the empty space.

This image shows a rendering of our chunk of artwork and the serial multiplier. The color selection is identical to the colors used to represent each layer in the tools we use - Mentor Graphics.

The image above shows what the artwork looks like in the Mentor Graphics layout tool.